Verilog Coding for Logic Synthesis артикул 2574e.
Verilog Coding for Logic Synthesis артикул 2574e.

Book DescriptionProvides a practical approach to Verilog design and problem solving * Bulk of the book deals with practical design problems that design engineers solve on a daily basis * Includes over 90 design examples * There are 3 full scale design examples that include specification, architectural definition, micro-architectural definition, озщли RTL coding, testbench coding and verification * Book is suitable for use as a textbook in EE departments that have VLSI courses.  Carolin2003 г 336 стр ISBN 0471429767.